Abhishek Patel
Qualcomm || Synopsys || Mtech VLSI Design, Nit kurukshetra
- Role
- Engineer at Qualcomm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Abhishek Patel
Hi folks, I am working as a Timing ECO CAD Engineer at Qualcomm. My work focuses on block-level timing closure using tools like PrimeTime, PrimeClosure, and Tweaker to analyze timing violations and implement ECO fixes while maintaining optimal PPA. I have a strong interest in physical design, timing optimization, and advanced VLSI Design implementation.
Experience
Engineer
Dec 2025 — Present · Bengaluru, IN
Education
National Institute of Technology, Kurukshetra, Haryana
Master of Technology - MTech, VLSI Design
University of Allahabad
Bachelor of Technology - BTech, Electronics and Communication engineering
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