Abhishek Mashetty

About Abhishek Mashetty

Experience in RTL DESIGN.Experience with Micro-architecture level design of IP blocks.Experience in RTL Development for various blocks in the Design.Support verification team on RTL verification.Worked on Static flows like Lint, CDC, LEC.Worked on Fishtail and Synthesis.Constraints development for CDC, Synthesis.Worked on Intel TFM’s with Cheetah-environment.Working knowledge with various FPGA’S Xilinx, Altera, and Synopsys.Working on FPGA boards and validating the design functionality.IP development in both ASIC/FPGA at SOC, Sub-system levels.Communicate and work with team members across multiple disciplines.Worked on projects like Hardware Accelerator, PCIE, CXL, SSD Controller.

Experience

1. Sr Design Engineer

   Analog Devices

   May 2024 — Present · Hyderabad, IN

Education

• Sri chaitanya Jr.college

  Intermediate, Maths,Physics,Chemistry

  2006 — 2008

• B.V.Raju Institute of Technology

  Master's Degree, Electronics and Communication Engineering with specilization as VLSI

  2013 — 2015

• Sarath Vikas High School

  High School, State board of Andhra Pradesh

  2005 — 2006

• Prof.Rama Reddy College of Engineering and Technology

  Engineer's Degree, Electrical, Electronics and Communications Engineering

  2008 — 2012

Skills

• Soc
• System on a Chip (Soc)
• Physical Design
• Dft
• Verification
• Perl
• Very-Large-Scale Integration (Vlsi)
• Microsoft Office
• Vlsi
• Verilog
• C
• Modelsim
• Field-Programmable Gate Arrays (Fpga)
• Vhdl
• Electronics
• Research
• Rtl Design
• Asic
• Application-Specific Integrated Circuits (Asic)