Abhishek M
RTL Design Engineer at Cadence
- Role
- Lead Design Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Abhishek M
Intern Design Engineer at Cadence Design Systems while pursuing M.Tech in VLSI Design and Embedded Systems.HDL Languages - Verilog, System Verilog.Protocol Knowledge - DDR, AXI.Have successfully developed and Implemented RTL using Verilog for given set of specifications. Carried out integration of the implemented blocks into the currently existing system.Carefully documented the developed RTL.
Experience
Lead Design Engineer
Jul 2024 — Present
Education
New Horizon College of Engineering
BE - Bachelor of Engineering, Electronic and Communications Engineering Technology
2013 — 2017
B. M. S. College of Engineering
Master of Technology - MTech, VLSI design and Embedded systems
2019 — 2021
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.