Abhishek Kumar Pal
Physical Design & STA Engineer | Intel | TSMC 3nm | Synopsys PrimeTime | Intel Caliber /Siemens Calibre | Tcl Automation | NIT Jalandhar
- Role
- Physical Design Intern at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Abhishek Kumar Pal
Physical Design & STA Engineer | Intel | TSMC 3nm | Synopsys PrimeTime | Intel Caliber/ Siemens Calibre | Tcl Automation | NIT JalandharAbout:Physical Design Engineer at Intel with a specialized focus on advanced nodes (TSMC 3nm).Expertise in Static Timing Analysis (STA) and Physical Verification. Proven track record in timing closure, having resolved 50+ setup/hold violations and improved WNS from negative slack to positive slack on critical SoC blocks.Performed Physical Verification Signoff using Siemens Calibre /Intel Caliber on TSMC 3nmDeveloped Tcl scripts to automate UCR debugging, reducing manual cycles.Technical Core:STA: PrimeTime ECO flows, SDC refinement)PV: Siemens Calibre / Intel Caliber (DRC, LVS)Automation: Tcl scripting for UCR/Violation analysisPassionate about solving complex PPA challenges in the evolving AI-silicon.Email : a••••••••@gmail.com
Experience
Physical Design Intern
Jul 2025 — Present · Bengaluru, IN
Technical Core:STA: PrimeTime ECO flows, SDC refinement)PV: Siemens Calibre / Intel Caliber (DRC, LVS)Automation: Tcl/Perl for reducing manual debug cycles
Education
Chhatrapati Shahu Ji Maharaj University (CSJMU), Kanpur
Bachelor of Technology - BTech, Electronics and Communications Engineering
2019 — 2023
Dr B R Ambedkar National Institute of Technology, Jalandhar
Mtech VLSI Design
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