Abhishek Kumar
Aspiring RTL Design & Verification Engineer | M.Tech in Signal Processing (2026), MNNIT Allahabad | Skilled in Verilog/SystemVerilog | Focused on Front-End Digital Design & ASIC Verification
- Role
- Indian Railways
- Location
- Prayagraj, UP, IN
- LinkedIn followers
- 500 followers
About Abhishek Kumar
Aspiring RTL Design & Verification Engineer with a strong foundation in digital…
Experience
Present
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.