Abhishek Bhatt

WORK HISTORY

EDUCATION

ABOUT ABHISHEK BHATT

Professional Experience Summary• Expertise in defining architecture, microarchitecture, and RTL coding.• Experience in linting, timing analysis, CDC, and power analysis, providing actionable feedback to enhance RTL quality design performance.• Skilled in defining RTL-level timing constraints to ensure accurate timing closure across clocks, I/O paths. • Experienced in design debug support to accelerate verification and delivery.• Strong understanding algorithm exploration,System C and MATLAB for high-level modelling, and System performance analysis.• Experienced in defining comprehensive verification test plans, code coverage analysis, and writing formal SystemVerilog Assertions (SVA).• Skilled in writing detailed Design Specifications, Application Notes, and other technical documentation supporting RTL development and verification.• Working on AI-assisted RTL code generation and automated timing constraint generation to improve design productivity and quality.Qualification:MS VLSI CAD(Manipal University,Manipal )Technical Skills: ASIC Design & Verification,STA, Design Flow Validation,Low Power VLSI DesignTechnical Languages: Verilog,VHDL,System Verilog,BSPICE,PERL,C/C++Tools: VCS,Design Compiler,BSPICE,HSPICE,Magic Layout,Modelsim,Xilinx ISE, Quartus.