Abhirup Lahiri
Principal Analog Circuit Designer at Marvell. Proven track record to create circuits with best figure-of-merit, 18 US granted patents.
- Role
- Principal Engineer at Marvell Technology
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Abhirup Lahiri
Inventor of 23 Patents (18 US patents granted) and first author of several papers in Solid State Circuits journals and conferences: JSSC, CICC, ESSCIRC. Over 16 years of design experience while working as an individual contributor, team leader and manager in European, American semiconductor companies in Switzerland, Ireland, France and India.Expertise in clock generation circuits, designed very wide range of analog circuits and systems. These include crystal oscillator, RC oscillator, LC-VCO, charge-pump PLL, ADPLL (TDC, DCO), CDR (analog, digital), DLL, Phase-interpolator, temperature sensor, baseband circuits for RF receivers like analog filters, analog VGAs, Rx Front end for Bluetooth LE (LNA, Mixer, complex IF filter), phase-shifters (ppf), band-gap reference, LDO, HDO, asynchronous digital LDO, buck converter, low distortion amplifiers, Continous Time Delta Sigma Modulator (CT-DSM), Asynchronous SAR ADC, Analog Front-End interface for magnetic sensor, clock duty cycle corrector, frequency doublers, GHz RF-DACs, DTC, phase interpolators, high linearity and high bandwidth ADC input drivers and sampling networks, injection locked and multi-phase clock generation circuits.
Experience
Principal Engineer
Jan 2024 — Present · Bangalore Urban, IN
Worked on wireline transceivers. Designed 12 GHz ADPLL for Custom D2D: TDC, DLF, DCO, regulators, bgr and PLL top VT budgeting.2. Built innovative DSP algorithms to improve link BER by orders of magnitude. Silicon verified proof of concept demonstrated for 224Gsps Ethernet link, two Patents filed. Architecting innovative very low jitter receiver clocking (PLL, distribution, CDR) for 425Gsps PAM6-8 Ethernet links. Also, working with teams in US, Canada on DSP. 3 patents filed on different aspects of improving jitter and link performance.
Education
Delhi University
Bachelors of Engineering, Electronics and Communications Engineering
2005 — 2009
Skills
- Physical Design
- Cadence Virtuoso
- Eda
- Ic
- Semiconductors
- Spectre
- Analog Circuit Design
- Mixed Signal
- Vco
- Integrated Circuit Design
- Analog
- Matlab
- Adcs
- Power Management
- Oscillators
- Verilog
- Pspice
- Very-Large-Scale Integration (Vlsi)
- Vlsi
- Vhdl
- Simulations
- Sensors
- Lna
- Cmos
- Asic
- Pll
- Radio Frequency (Rf)
- C
- Soc
- Filters
- Spice
- Static Timing Analysis
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