Abhiram Bindigan
Design Intern at Intersil || Actively Looking for a Full Time Position in Digital ASIC Design and Verification
- Role
- Design Engineer Intern at Intersil Acquired By Renesas
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Abhiram Bindigan
OBJECTIVE To pursue a Full Time opportunity in Digital ASIC Design and…
Experience
Design Engineer Intern
Jun 2014 — Present
Skills
- Vlsi
- Soc
- Labview
- Altera Quartus
- Verilog
- Fpga
- Xilinx
- Algorithms
- Microsoft Office
- C
- Ic
- Testing
- Xilinx Ise
- Rtl Verification
- Systemverilog
- Logic Synthesis
- Static Timing Analysis
- Python
- Debugging
- Rtl Design
- Cadence
- Semiconductors
- Modelsim
- Matlab
- Linux
- Asic
- Vhdl
- Synopsys Tools
- Cadence Virtuoso
- Perl
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