Abhinav Tiwari

About Abhinav Tiwari

Have around approximate 18 years of overall experience in VLSI front end involving Verification, Validation and Emulation. • Experienced in Model bring up for all the industry Tool i.e Pallidium,/Veloce/ Zebu both at IP and SOC Level.• Worked on accelerating UVM based environment to port in Emulation using Mentor Graphics Veloce/TBX flow. • Exposure of using Debugger Lauterbach.• Integrated Virtual JTAG Transactor for reducing the dependency of external H/W and clock Halt along with that using the solution CODELINK for processor debug to correlate the S/W and H/W debug.• Worked on SystemC, UVM based verification Environment.• SCE-MI based transactors profiling.• Exposure to HVL SystemVerilog and E, Involved in the development and modification of UVC/EVC.• Good knowledge of using Hardware development boards with FPGA’s for validation.• Worked on Automotive protocol like CAN and Flex ray.• Knowledge of Bus Protocol like AMBA/AXI• Team management, mentoring juniors.

Experience

1. Engineering Manager

   Intel

   Jun 2020 — Present

Education

• Coer

  Btech, Electronics

  2002 — 2006