Abhinav T.
Verification and Validation Engineer at Microsoft
- Role
- Verification and Validation Engineer at Microsoft
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Abhinav T.
In constant pursuit of achieving expertise in RTL Design Verification- Design Verification Engineer at Marvell Semiconductor, graduated from San Jose State University as an Electrical Engineer, with specialization in ASIC/SoC Design and Verification.Technical Proficiency: Verification - SystemVerilog, UVM, Testbench Design, Assertions, Coverage.Formal Verification - SVA, Formal model checking - FCA, FV_CC, XPROP, Scoreboading. Design - RTL Design, Synthesis, Logic Design, Cross Domain Crossing, STA.Physical Design - Floor Plan, Power grid design, Pin placement, CTS, Routing, RC extraction, DRC/LVS.Computer Architecture - MIPS architecture, Pipelining, Branch Prediction, Instruction-level parallelism, Multi-level caches, Cache Coherence.Industry Standards - Ethernet, Fibre Channel.
Experience
Verification and Validation Engineer
Aug 2022 — Present · Mountain View, CA, US
Education
UCSC Silicon Valley Extension
VLSI Engineering, Functional and Formal Verification
2018 — 2018
San José State University
Master of Science - MS, Electrical and Electronics Engineering
2017 — 2018
Anna University Chennai
Bachelor's degree, Electrical, Electronics and Communications Engineering
2012 — 2016
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