Abhinav Sethi
- Role
- Senior Design Verification Engineer at Arm
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Abhinav Sethi
Skilled in Universal Verification Methodology, System Verilog, CPU microarchitecture…
Experience
Senior Design Verification Engineer
Nov 2019 — Present
Skills
- Application-Specific Integrated Circuits (Asic)
- Systemverilog
- Nand Flash
- Field-Programmable Gate Arrays (Fpga)
- Static Timing Analysis
- Embedded Systems
- System on a Chip (Soc)
- Rtl Design
- Microcontrollers
- Verilog
- Vhdl
- Logic Synthesis
- C
- System Verilog
- Linux
- Matlab
- Very-Large-Scale Integration (Vlsi)
- Algorithms
- Rtl Verification
- Digital Image Processing
- Programming
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