Abhinav Kidambi
- Role
- Mts Silicon Design Enginner at AMD
- Location
- Fort Collins, CO, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Abhinav Kidambi
2+ years of experience in ASIC and soc verification. • Experience with UVM…
Experience
Mts Silicon Design Enginner
Oct 2020 — Present
Skills
- Java
- Unix
- Verilog
- Functional Verification
- Perl
- Altera Quartus
- Interfaces
- Formal Verification
- Sas
- Systemverilog
- Python
- Cmos
- Ssd
- Universal Verification Methodology (Uvm)
- Uvm
- Application-Specific Integrated Circuits (Asic)
- C
- Raid
- System Administration
- C++
- Eclipse
- Assertion Based Verification
- Rtl Coding
- .net
- Mac Os X
- Nios Ii
- Linux
- Modelsim
- Assertions
- Ms Office Suite
- Microsoft Office
- Cadence Virtuoso
- Doxygen
- Rtl Design
- Digital Electronics
- Mysql
- Asic
- Sata
- System Verification
- Ubuntu
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