Abhinav Bhatt

About Abhinav Bhatt

Expertise in leading ASIC physical design teams for successful multiple tapeouts across different tech nodes.Strong and proven technical leadership in bringing differentiation to ASIC\'s catering to various markets viz. Mobile communication and Networking with multiple foundries.Goal oriented with attention to detail approach.Skill Set :ASIC flow : RTL2GDSII, Physical Design, Timing Closure, Physical VerificationHDL : Verilog and VHDLTechnology : 14nm, 16nm, 28nm, 45nm, 65nm and 90nmSynthesis tools : Synopsys Design Compiler/DC-topo, Cadence RTL CompilerPnR tools : Synopsys IC Compiler, Synopsys ICC2, Magma Talus, Cadence EDIExtraction tool : Synopsys Star-xtTiming Closure : Synopsys Primetime-SIPV tools : Synopsys Hercules and Mentor Graphics CalibreStatic/Dynamic IR tools : Apache RedhawkScripting Languages : Awk, Perl, Tcl

Experience

1. Director - Physical Design

   Accenture

   Feb 2025 — Present

Education

• Bit Mapper integration technologies private limited

  PG diploma, vlsi design

  2001 — 2002

• College Of Technology, G.B.P.U.A&T, Pantnagar

  B.Tech, Electronics and Communication Engineering

  1997 — 2001

Skills

• Lvs
• Application-Specific Integrated Circuits (Asic)
• Physical Verification
• Magma
• Asic
• Tcl
• Hercules
• Digital Design
• Physical Design
• Drc
• Logic Synthesis
• Primetime
• Vlsi
• Low-Power Design
• Integrated Circuit Design
• Low Power Design
• Timing Closure
• Cmos
• Semiconductors
• Verilog
• Vhdl
• Very-Large-Scale Integration (Vlsi)
• Floorplanning
• Clock Tree Synthesis
• Mixed Signal
• Static Timing Analysis