Abhilash U

PDK Enginner @ Intel

Role
Pdk Engineering Intern at Intel
Location
Shivamogga, KA, IN
LinkedIn followers
500 followers

About Abhilash U

I have experience in defining the high-level architecture and specifications for VLSI designs, considering factors such as performance, power consumption, and area constraints.I can create Register Transfer Level (RTL) designs using hardware description languages (HDLs) like Verilog. This involves designing the functional blocks, datapaths, control units, and interfaces of the VLSI circuit. I have experience in developing testbenches to verify the correctness and functionality of the RTL design. This involves creating test stimuli, applying them to the design, and checking the outputs against expected results.My contribution to project : I have created the schematic of the Sense Amplifier using Cadence tools such as Virtuoso. This involves designing the transistor-level circuitry, biasing circuits, and interconnections necessary for the Sense Amplifier operation. You would have ensured proper sizing and connectivity of the components, considering the design specifications and requirements.Layout Design: I have been involved in the layout design of the Sense Amplifier using Cadence\'s layout editor, such as Virtuoso Layout Suite. This involves converting the schematic design into a physical layout, optimizing the placement and routing of the components to minimize parasitic effects and ensure manufacturability. Also I have adhered to design rules and guidelines provided by the foundry.I have access to a vast amount of information and knowledge on VLSI design and semiconductor technologies. This includes various design methodologies, fabrication processes, circuit optimization techniques, and verification methodologies. I can provide valuable insights and assistance across different aspects of the job.I can quickly learn new concepts and stay updated with the latest advancements in VLSI and semiconductor fields. This adaptability allows me to understand and address emerging challenges and technologies.

Experience

  1. Pdk Engineering Intern

    Intel

    Jul 2025 — Present · Bengaluru, IN

Education

  • Jawaharlal Nehru National College of Engineering

    Bachelor of Engineering -BE, Electronics and Communication Engineering

    2019 — 2023

  • Adichunchanagiri Pu College

    Pre University Certificate, PCMB

    2017 — 2019

  • Vellore Institute of Technology (VIT)

    Master of Technology - MTech, VLSI

  • ST.charles high school

    Secondary School Leaving Certificate

    2007 — 2017

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Abhilash U — Pdk Engineering Intern at Intel in Shivamogga, KA, IN | Unifers