Abhilash Srivastava

About Abhilash Srivastava

I have over 7 years of experience working on digital design/verification. Currently, working as SOC DFT Engineer in Intel corporation and working on scan validation, also worked on TAP validation in the same team. Intel CPU contains a large number of JTAG TAPs and IJTAG registers and all the TAPs are connected in form of a network, I validate the TAP network whether all TAPs are functional, all its registers are working and also checks the securities. I worked as Senior Design Engineer in ST Microelectronics in past, developed and improved MBIST IP for our customers. I also gave support to the customers who were using our MBIST IP. I also did improvements in the MBIST IP by taking feedbacks from the customers. Most of the time, Challenges faced by the customers gave us the direction to improve IP. I was an intern in the same group earlier where I have worked on the high performance fully programmable digital sin gen design and ADC modeling. I have faced many challenges working on sine generator and these challenges make me good on designs. Fortunately, I had got the good silicon validated result of the sin gen by continuously working on them.

Experience

1. Soc Dft Engineer

   Intel

   Jan 2022 — Present · Bengaluru, IN

   Validating CPU scan chain network, our goal is to make the scan chain network ready for actually ATPG pattern by validating lots of signal there.Validating CPU TAP network which contains a large number of JTAG TAPs and IJTAG registers Validating whether all TAPs are functional, all its Data/Instruction registers are working and also checks the securities.Collaborate with RTL team to fix the debugged issue.Developing/Updating testcases during validation if required.Developing/Updating collaterals for validation if needed.Debug the cases using Verdi tool.Supporting internally to the DFX team if there is any issue related to TAP network.

Education

• BUNDELKHAND INSTITUTE OF ENGINEERING AND TECHNOLOGY, JHANSI

  B.Tech, Electronics and Communications Engineering

  2011 — 2015

• Indian Institute of Technology, Patna

  Master of Technology, VLSI & Embedded Systems

  2017 — 2019