Abhilash Eyyapu

About Abhilash Eyyapu

Skills-> ASIC frontend verification planning and coverage driven closures-> System verilog based verification using UVM and OVM methodologies-> System Verilog Assertions-> Perl scripting for automation of simulations/regressions/coverageDomain Knowledge-> AMBA APB, AXI and AHB-> WLAN MAC 802.11n -> Good knowledge in DDR4 and HBM-> Basic knowledge in PCI Express - TLP LayerProject experiece:Oct\'2011 to Feb\'2012:At Aceic-> Developed in house OVM and UVM testbench environments to verify SPI, UART Cores-> Explored OVM and UVM methodologies.March\'2012 to Apr\'2013 (For verification services from ACEIC)-> Worked in MAC IP ownership project-> MAC 802.11n and 802.11ac IP level verification using UVM methodology-> Verification of AXI master and AXI slave RTLs using Cadence Denali AXI VIP in UVM-> Developed AXI and AHB slave models.May\'2013-Jan\'15(For verification services from ACEIC)-> Working in WLAN 802.11 MAC SoC verification using system verilog based UVM methodology, from planning to sign off-> Developed testbench environment for PCIe to verifiy MAC core in SoC using PCIe as interface.Feb\'2015-Jun\'15(For verification services from ACEIC)-> Developed PCIe based UVM environment using Cadence PCIe VIP. Integration and bringing up the tests for PCIe EP - RC IPs in an SoC, from planning to sign off.Jul\'15-Dec\'12(For verification services from ACEIC)-> DDR4 PHY Test chip verification, from planning to sign off, using UVMJan\'16-May\'16(For verification services from ACEIC)-> Multi(Ethernet/PCIe/CEI) purpose gigabit SERDES PHY Test chip verification, from planning to sign off, using UVMJun\'16-Sep\'16(For verification services from ACEIC)-> HBM PHY multichannel IP Verification

Experience

1. Principal Engineer

   Infineon Technologies

   Sep 2021 — Present · Bengaluru, IN

   Majority ownership of WLAN MAC DV at IP level.Leading WLAN MAC+PHY DV at Sub system level.Experience in developing UVM based testbenches along with integration at sub system level.RTL, GLS and Low power DV closure for MAC IP.

Education

• Andhra University

  M.Sc(Tech) VLSI Design, VLSI

  2008 — 2011

• Andhra University

  B.Sc, (Maths, Electronics, Computers)

  2005 — 2008

Skills

• Open Verification Methodology
• Ncsim
• Rtl Coding
• Amba Axi
• Ovm and Uvm Verification Methodologies
• Vlsi
• Amba Ahb
• Verilog
• Modelsim
• Systemverilog
• Wlan
• Functional Verification
• Assertion Based Verification
• Uvm
• Verdi