Abhijit Joshi

About Abhijit Joshi

Driven by a passion for building future compute. I am a CPU RTL Design Engineer specializing in high-performance, power-efficient microarchitecture. From architecting pipelined RISC-V cores to optimizing custom ALUs and memory subsystems, I thrive at the intersection of digital logic, innovation, and silicon realization. With hands-on expertise in Verilog/SystemVerilog, FSM design, and advanced pipelining, I have contributed to RTL IPs for CPUs, AXI interfaces, and cache hierarchies. My workflow spans the full silicon lifecycle-from microarchitecture definition and RTL coding to synthesis, timing closure, and seamless handoff to physical design teams Strong engineering professional with a Master of Technology (M.Tech.) focused in Electrical Engineering from Indian Institute of Technology, Bombay.

Experience

1. Senior Cpu Design Engineer

   NVIDIA

   Jan 2024 — Present · Bengaluru, IN

Education

• Indian Institute of Technology, Bombay

  Master of Technology (M.Tech.), Control & Computing

  2009 — 2012

• Visvesvaraya National Institute of Technology

  Bachelor of Technology (BTech), Electrical and Electronics Engineering

  2005 — 2009

Skills

• Rtl Design
• Synopsys Primetime
• C
• Microsoft Office
• Vlsi
• Verilog
• Synopsys Design Complier
• Verdi
• Matlab
• Low-Power Design
• Conformal Lec
• C++
• Unix