Abhijeet Barua

Device Physics | Integration | Yield Analysis | Foundry Logic Technology Development

Role
Ltd Staff Module and Integration Yield Engineer at Intel
Location
Portland, OR, US
LinkedIn followers
500 followers

About Abhijeet Barua

Semiconductor professional with 4+ industry and 9+ years of collective experience in:• Device physics, yield analysis, modeling, scaling for both thin film logic & NVM devices• Statistical analysis of device/e-test/reliability (TDDB, TZDB, HCI, RTN, BTI, SCE) data through DOE on MATLAB/Python/JMP & automated testbenches• Authored/co-authored 45+ white papers for process development/continuous improvement projects, & principal contributor in 5+ critical task forces at Intel• Development, integration, & technology transfer of next-generation Super Compute Silicon chip assembly technologies & data driven roadmap at Intel• End-to-end DOE, data mining, data analysis, & SPC for metallization, films, & resistivity modules/toolsets within specific process flows• Silicon & oxide semiconductors, MIM/MIS/MOS architectures, device physics, TFT array design & processes, advanced integrated circuits & systems, advanced CMOS devices• Nanotechnology development in Class cleanroom on amorphous oxide semiconductor TFT, FeFET, RRAM, & MEMS topologies• Vacuum deposition (PVD/CVD), nanofabrication, device TCAD, SPICE, modeling, & simulation• Design, development, systematic characterization, & performance optimization of a-InGaZnO4/ZnO TFTs & circuits, SPC for transistor performance, RTN, BTI, parasitic parameters, & extensive statistical analysis in MATLAB/Python• Effects of plasma/anneal treatment, passivation, metal contact, & device structure on device characteristics & stability• Material characterization on SEM, EDX, AFM, VASE, contact angle metrology, & ATR-FTIR spectroscopy

Experience

  1. Ltd Staff Module and Integration Yield Engineer

    Intel

    May 2024 — Present · Portland, OR, US

    Development & pathfinding of sub-3nm FEOL logic & MOL memory thin film process technologies to improve device performance for Intel\'s leading-edge five-nodes-in-4-years (5N4Y) roadmaps on Intel 4, 3, 20A, 18A, 14A & beyond.

Education

  • University of Cincinnati - College of Engineering and Applied Science

    Doctor of Philosophy - PhD, Electrical Engineering & Computer Science

    2016 — 2021

  • University of Cincinnati

    Doctor of Philosophy - PhD, Electrical Engineering & Computer Science

    2016 — 2021

  • National Institute of Technology Rourkela

    Bachelor of Technology - BTech, Electrical Engineering

    2007 — 2011

Skills

  • Microsoft Office
  • Power Plants
  • Verilog
  • Pspice
  • Ni Multisim
  • Electrical Engineering
  • C++
  • Engineering
  • Nanoelectronics
  • Vhdl
  • Solidworks
  • Matlab
  • Autocad
  • H-Spice
  • Powerpoint
  • Microsoft Excel
  • Orcad
  • Ni Labview
  • Electronics
  • Microsoft Word
  • Autodesk Inventor
  • C
  • Programming

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Abhijeet Barua — Ltd Staff Module and Integration Yield Engineer at Intel in Portland, OR, US | Unifers