Abhijeet Jadhav
Senior Design Verification Lead at Apple
- Role
- Senior Design Verification Lead at Apple
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Abhijeet Jadhav
Design Verification and Reference Modeling of Ethernet Packet Processor and Router Packet Policers 10G/1G MAC, PCS, WIS Data Center Asics Fibre channel Switch Video Decoder/Encoder (H.264), Post ProcessingSkills Test plan creation, Functional Verification, Functional/Code coverage, Constraint Random Verification, Testbench Development, Verification Architecture, Reference Modeling, RTL design. Expertise in Verilog, System Verilog, System C, C++ and Universal Verification Methodology (UVM). Reference Modeling using C++ and System C. Perl Scripting
Experience
Senior Design Verification Lead
Oct 2021 — Present · Cupertino, CA, US
Education
Indian Institute of Technology, Kharagpur
M.Tech., Microelectronics and VLSI Design
2004 — 2006
University of California, Berkeley, Haas School of Business
Master of Business Administration - MBA, Business Administration and Management, General
Skills
- Debugging
- Rtl Coding
- Soc
- Logic Synthesis
- Uvm
- H.264
- Functional Verification
- Systemc
- Vlsi
- Fpga
- Asic
- Systemverilog
- C++
- Perl
- Eda
- Verilog
- Rtl Design
- Ethernet
- Digital Signal Processors
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