Abhijeet Jadhav

About Abhijeet Jadhav

I Have Total 18 plus years of experience under Hardware ASIC VLSI Front End Verification domain andI am a Certified Scrum Master. I have Worked in SW side under Performance Testing Side and was responsible for customer contact and operations activityWorked in VLSI domain with proficiency in1. Verilog HDL/VHDL / VERA /System Verilog.2. Module level /Full Chip verification.3. Writing BFM in Verilog HDL/VHDL/VERA /System Verilog.4. Writing verification component like Driver,Checker, Scoreboard & Monitor.5. Test / Verification plan development.6. Functional Coverage, Fault Coverage.7. RTL Coding.8. OOP concepts.9. Assertion based verification (SVA), processor based verification and validation, PLI linking.10. Post silicon debug.11. Validation by Xilinx FPGA Board and debugging through Chip Scope/ LA.12.UVM, VMM, OVM.Specialties: SOC Verification/Validation, Functional Verification, Coverage,Fault Coverage and Performance Verification,Have proficiency in System Verilog/Verilog HDL/VHDL and also used various range of EDA tools likeVERILOG-XL / NC-VERILOG, VCS, SCIROCCO, MODELSIM, VERFIAULT, DEBUSSY, SIMVISION, VIRSIM. I am a Certified Scrum Master.

Experience

1. Silicon Engineering Manager

   Accenture

   Feb 2025 — Present

Education

• Bharat English School (S.S.C.), N Wadia College (H.S.C.), Savitribai Phule Pune University ( Masters )

  Masters, Electronics

  1992 — 1999

Skills

• Ncsim
• Verilog
• Asic
• Functional Verification
• Debugging
• Soc
• Modelsim
• Vlsi
• Open Verification Methodology
• Eda
• Rtl Coding
• Systemverilog