Abhay Kumar Tyagi
SOC Design Manager at INTEL
- Role
- Design Manager at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Abhay Kumar Tyagi
Excellent hand-on in ASIC Physical design. Major area of working are as follow.1. Floorplanning.2. Placement and CTS build3. Routing and SI analysis.4. ECO generation and timing fixes.5. LVS, DRC and ERC fixes.6. Post Layout Static Timing Analysis and Timing Closure.7. Gate Level ECO implementations.8. Signal Integrity Analysis.9. Static and Dynamic IR Drop Analysis.10. Physical Verification (DRC, LVS)11. QRC Parasitic Extraction12. CLP validation for CPF aware multi-voltage design.Scripting languages : shell, awk, exposure of PERL & TCL. Good exposure to PERL and TCL scripting language.Experience on 90nm, 45nm, 28nm, 22nm, 20nm Exposure on 45nm, 28nm & 20nm Technology with multivoltage domain (CPF aware)Specialties- Expert for Netlist to GDSII ASIC design flow.
Experience
Design Manager
Aug 2022 — Present
Education
BIT Mesra Student-Industry Relations Cell
Master of Engineering, Microelectronics
2005 — 2007
Birla Institute of Technology and Science, Pilani
ME
2005 — 2007
Skills
- Physical Design
- Asic
- Lvs
- Soc
- Drc
- Tcl
- Cmos
- Physical Verification
- Timing
- Floorplanning
- Perl
- Timing Closure
- Static Timing Analysis
- Primetime
- Application-Specific Integrated Circuits (Asic)
- Integrated Circuit Design
- Design Rule Checking (Drc)
- Very-Large-Scale Integration (Vlsi)
- Layout Versus Schematic (Lvs)
- System on a Chip (Soc)
- Digital Signal Processors
- Signal Integrity
- Debugging
- Integrated Circuits (Ic)
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