Abel Mathew Varghese
SoC PD at Apple | UMN | VIT
- Role
- Soc Physical Design Engineer at Apple
- Location
- Minneapolis, MN, US
- LinkedIn followers
- 500 followers
About Abel Mathew Varghese
An Electrical and Computer Engineering graduate student at the University of Minnesota, Twin Cities, in search of attaining expertise in the field of Physical Design, PD CAD, and Static Timing Analysis.•I\'m actively seeking full time opportunities in Physical Design, Methodology starting May 2024.• Circuit and Physical Design Tools: Cadence [Virtuoso - Schematic and Layout, Innovus], Synopsys [ICC2].• Synthesis and Simulation Tools: Synopsys Design Compiler, Cadence Genus, Synopsys HSPICE, Synopsys VCS, Cadence Xcelium.• Timing/Signoff Tools: Synopsys PrimeTime.• Programming and Scripting Languages: C/C++, Python, TCL scripting, shell scripting.• Additional Skills: Custom IC Design, Automatic Place and Routing, RTL2GDS, SPICE Simulation, 7nm ASAP 7 PDK, Low Power Design, Static Timing Analysis, FinFETs, Physical Design Flow.
Experience
Soc Physical Design Engineer
Jul 2024 — Present · Austin, TX, US
Education
Lourdes Public School and Junior College - India
CBSE Higher Secondary - 12th
2014 — 2016
University of Minnesota
Master of Science - MS
2022 — 2024
Vellore Institute of Technology
Bachelor of Technology - BTech
2016 — 2020
Mar Baselios Public School - India
CBSE 10th
2003 — 2014
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