Abdul Latheef Abdul Kalam

About Abdul Latheef Abdul Kalam

RTL Design Engineer with around 14 years of experience in the field of FPGA/ASIC/SoC using Verilog HDL, System Verilog and VHDL.

Experience

1. Staff Engineer

   Microchip Technology Inc.

   Aug 2023 — Present · Chennai, IN

Education

• KSOU

  Master of Technology (MTech), Electrical, Electronics and Communications Engineering

  2013 — 2014

• Anna University Chennai

  Engineer's Degree, Electronics And Communication Engineering

  2005 — 2009

Skills

• Xilinx Edk
• Tcl
• Vhdl
• Vivado Ide
• Verilog Hdl
• Xilinx Ise
• Xilinx Coregen
• Perl
• Altera Quartus
• Hardware Diagnostics
• Modelsim
• Fpga Prototyping
• Questasim
• C
• C++
• Xilinx Vivado Ide
• Rtl Design
• Verilog