Aashish Sadri

Ip Silicon Design and Automation Engineer @Xilinx

Hyderabad, IN

Running Tests for checking the functionality of the IPs on Viper Environment and coding PERL, TCL Scripts to enhance the workflows for Viper Development to test the various configuration of IPs• Triggering the Regression Runs and generating, analyzing the Timing, Area, Power, bit-stream reports for the Runs through an Automation Setup Tool Jenkins coded in Shell Script.• Debugging and solving the failures in IP Design, verification test-benches parts of the designs, running different tests on Vivado Tool using Xilinx XSIM, Synopsys and VCS Simulators• Working in the Design Team of AXI, GT_QUAD, Smart-Connect Embedded IPs for the design and maintenance of Blocks used in the Design Architecture coded in Verilog, SV and VHDL