Aarti Rane

SOC Design Engineer | Electrical and Electronics Engineering

Role
Soc Design Engineer at Altera
Location
Hillsboro, OR, US
LinkedIn followers
500 followers

About Aarti Rane

I am passionate with working on design and microarchitect high-performance digital hardware.My work spans custom memory engines, DMA pipelines, graphics display IP, and ARM-based interrupt controllers. I build scalable, timing-optimized RTL that integrates cleanly and supports efficient validation—ensuring designs are not only performant but also debug-ready and system-aware.At Intel, Altera, and GlobalFoundries, I’ve contributed to successful tape-outs, led post-silicon debug efforts, and collaborated across architecture, synthesis, and verification teams. I’ve refined register verification flows, developed integration strategies for complex IP blocks, and resolved silicon issues from PCIe loopback to power-on sequencing.🧠 What I bring- RTL and microarchitecture expertise across compute and SoC domains- Verification-aware design practices that streamline integration and debug- Strong debugging instincts—from waveform analysis to timing closure- Cross-functional fluency across design, architecture, and post-silicon teams Core Skills: RTL Design Microarchitecture Verification Integration Silicon Debug ARM Protocols STA CDC Display & Memory SubsystemsIf you\'re building high-performance silicon and need a designer who works hard delivers clean, scalable logic with an enthusiasm to learn —I’d love to connect.

Experience

  1. Soc Design Engineer

    Altera

    May 2023 — Present

Education

  • Portland State University

    Master of Science (MS), Electrical and Electronics Engineering

  • Vidyalankar Institute Of Technology

    Bachelor of Engineering (B.E.), Electrical and Electronics Engineering

    2011 — 2015

Skills

  • Electronics
  • Microsoft Word
  • Universal Verification Methodology (Uvm)
  • Microsoft Excel
  • Powerpoint
  • Leadership
  • Questa Sim
  • Linux
  • Ni Multisim
  • Microsoft Powerpoint
  • English
  • Html
  • Python
  • Systemverilog
  • Verilo
  • Engineering
  • Multisim
  • Windows
  • Research
  • C
  • Programming
  • Microsoft Office
  • Vhdl
  • Matlab
  • Xilinx Vivado
  • C++
  • Linux Scripting
  • Verilog
  • System Verilog
  • Cadence Virtuoso
  • Public Speaking
  • Labview
  • Keil
  • Teamwork
  • Perl
  • Embedded Systems

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Aarti Rane — Soc Design Engineer at Altera in Hillsboro, OR, US | Unifers