Aarti Ramesh
ASIC Physical Design Engineer at Meta
- Role
- Asic Physical Design Engineer at Meta
- Location
- Menlo Park, CA, US
- LinkedIn followers
- 500 followers
About Aarti Ramesh
Physical Design Engineer with 13+ years of professional experience involving multiple tapeouts in advanced technology nodes. Strong background in all stages of ASIC physical design flow - Floorplanning, power planning, place and route, clock tree synthesis, static timing analysis, EM/IR analysis and physical verification.
Experience
Asic Physical Design Engineer
Jan 2019 — Present · San Francisco, CA, US
Building hardware accelerator chips to support Meta’s infrastructure needs.
Education
College of Engineering, Guindy
B.E, Electrical and Electronics Engineering
Texas A&M University
M.S, Computer Engineering
Skills
- C++
- Spice
- Logic Design
- Asic
- C
- Programming
- Vlsi
- Computer Architecture
- Circuits
- Verilog
- Physical Design
- Digital Ic Design
- Custom Circuit Design
- Soc
- Matlab
- Cadence Virtuoso
- Eda
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