Aaron D Araya
Experienced Silicon Validation Engineer at Microsoft | Specialist in SI/PI & Post-Silicon Debug | LPDDR5/DDR5 & PCIe Gen 5/6 | PythonSV Automation | Intel Division Recognition Award Winner
- Role
- Electrical Validation i o, Verification, and Silicon Validation Engineer at Microsoft
- Location
- Portland, OR, US
- LinkedIn followers
- 500 followers
About Aaron D Araya
I bridge the gap between pre-silicon theory and post-silicon reality through deep technical expertise.Currently at Microsoft, I am experiencing the front lines of Electrical Validation (I/O) and Silicon Verification for high-performance server platforms. My career is defined by a mastery of Signal Integrity (SI) and Power Integrity (PI), ensuring that complex interfaces like LPDDR5, PCIe, CXL, and UCIe perform flawlessly under real-world conditions.With over 7 years of industry experience—including my significant tenure at Intel—I have become a go-to specialist for complex system-level debugging and hardware characterization.Areas of Expertise:• Advanced Debugging: Utilizing high-end lab instrumentation (Oscilloscopes, BERT, TDR) to root-cause hardware regressions and system-level crashes.• Technical Automation: Leveraging PythonSV to transform manual validation into high-throughput automated suites, significantly accelerating data analysis.• Ecosystem Collaboration: Partnering with industry leaders like Samsung, SK Hynix, and Micron to ensure JEDEC compliance and optimize system margins.Key Recognition: Recipient of the Intel Division Recognition Award (2024) for excellence in Silicon Engineering and cross-functional problem-solving.
Experience
Electrical Validation i o, Verification, and Silicon Validation Engineer
Dec 2025 — Present · Hillsboro, OR, US
Electrical Validation I/O & Silicon Validation Engineer• Experiencing the full lifecycle of End-to-End (E2E) validation for high-frequency server platforms, specializing in CXL,PLL, PCIe, and UCIe architectures.• Driving system bring-up and silicon verification using advanced SerDes architectures and CRD/retimer solutions.• Performing deep-dive SI/PI analysis to ensure robust, standards-compliant, and high-performance system operation across the full stack.
Education
Oregon Institute of Technology
Pursuing of a Master of Electrical Engineering , Embedded System Hardware.
2020 — 2022
Phoenix College
Associate's degree, Engineering
2009 — 2011
Ira A. Fulton Schools of Engineering at Arizona State University
Electrical and Electronics Engineering
2011 — 2014
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