Aalok Panvalkar
Lead Applications Engineer at Cadence Design Systems
- Role
- Lead Application Engineer at Cadence
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Aalok Panvalkar
Majors: Computer Architecture and DesignDesign Verification and ValidationCoursework: 1. Application Specific Integrated Circuit (ASIC)2. Computer Architecture 3. Introduction to System-Verilog4. Emulation and System specific verification (UVM)5. Pre-Silicon Validation6. Advanced Computer architecture - 17. Formal verification (HW/SW System) Technical Skills:Hardware Description Language: SystemVerilog, Verilog EDA Tools: Mentor’s Veloce Emulator, Mentor’s QuestaSim, Synopsys Design Compiler (DC), SAT Solver, Cadence, Composer schematics, Cadence Virtuoso, Mentor’s ModelSim, EAGLE, Keil, Xilinx suite. Programming Languages: TLA,Python scripting, C, C++, 8085 & 8051 Assembly Language
Experience
Lead Application Engineer
Sep 2020 — Present · San Jose, CA, US
Education
Vivekanand Education Society's Institute Of Technology
Bachelor's degree, Electronics Engineering
2013 — 2016
Portland State University
Master’s Degree, Electrical and computer engineering
2016 — 2018
Vivekanand Education Societys Institute of Technology Sindhi Society Chembur Mumbai 400 071
Engineering Diploma, Electronics and Communication Engineering
2010 — 2013
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