Aakil Bapna

About Aakil Bapna

RTL design engineer with 9+ years of experience in micro architecture, ip block design, low power design,RTL coding, debug, Lint & CDC check.

Experience

1. Staff Engineer

   Qualcomm

   Dec 2023 — Present · Karnataka, IN

Education

• Centre for Development of Advanced Computing (C-DAC)

  Pgdm, Vlsi

  2017 — 2017

• SRM University

  Master of Technology (M.Tech.), VLSI Design

  2013 — 2015

• Agnel Polytechnic

  Diploma In Engineering, Industrial Electronics

  2005 — 2009

• DY Patil Institute Of Engineering And Technology

  Bachelor of Engineering (BE), Electrical, Electronics and Communications Engineering

  2009 — 2012

Skills

• Electronics
• Cadence Pspice Ad
• Perl
• Power Electronics
• Hspice
• Verilog Hdl
• Microwind
• Logic Synthesis
• Control Systems Design
• Application-Specific Integrated Circuits (Asic)
• Vhdl
• System Verilog
• System on a Chip (Soc)
• Rtl Design
• Field-Programmable Gate Arrays (Fpga)
• Xilinx 13.1
• Project Management
• Integrated Circuit Design
• Rf Analog & Mixed Signal Processing
• Vlsi
• C
• Systemverilog
• Advanced Modelism