Aaditya Goyal
Design Verification Engineer at Ampere
- Role
- Principal Verification Engineer at Ampere
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
Information TechnologyView LinkedIn profile
Experience
Principal Verification Engineer
Sep 2021 — Present · CA, US
Education
Indian Institute of Technology, Mandi
Bachelor's degree, Electrical, Electronics and Communications Engineering
2009 — 2013
Texas A&M University
Master of Science (M.S.), Computer Engineering
2016
Skills
- Field-Programmable Gate Arrays (Fpga)
- Matlab
- Python
- Powerpoint
- Microsoft Excel
- Computer Architecture
- Proteus
- Integrated Circuit Design
- Winspice
- Verilog
- Xilinx Ise
- Cadence Virtuoso
- Rtl Design
- Machine Learning
- Nc-Verilog
- Cadence Simvision
- C++
- C
- Java
- Sql
- Vmanager
- Linux
- Modelsim
- Synopsys Primetime
- Microsoft Office
- Cadence Spectre
- Assembly Language
- Electronics Hardware Design
- Synopsys Design Vision
- Application-Specific Integrated Circuits (Asic)
- R
- Microsoft Word
- Data Analysis
- Mips Instruction Set
- Cadence Virtuoso Layout Editor
- Vplanner
- Very-Large-Scale Integration (Vlsi)
- Jmp
- Testing
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